A D V A N C E I N F O R M A T I O N
remains the same for the initial delay setting with the
Burst Access Timing Control
exception that data is valid after the falling edge.
In addition to the IND/WAIT# signal control, burst con-
trols exist in the Control Register for initial access de-
lay, delivery of data on the CLK edge, and the length
of time data is held.
Table 7. Burst Initial Access Delay
Initial Burst Access
(CLK cycles)
Initial Burst Access Delay Control
54D, 68D,
CR13 CR12 CR11 CR10
64C, 65A
80C, 90A
The Am29BDD160 contains options for initial access
delay of a burst access. The initial access delay has
no effect on asynchronous read operations.
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
3
4
Burst Initial Access Delay is defined as the number of
clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of
ADV#) until the first valid CLK edge when the data is
valid.
5
6
7
8
The burst access is initiated and the address is
latched on the first rising CLK edge when ADV# is ac-
tive or upon a rising ADV# edge, whichever comes
first. (Table 7 describes the initial access delay config-
urations.) If the Clock Configuration bit in the Control
Register is set to falling edge (CR6 = 0), the definition
9
10
1st CLK
2nd CLK
3rd CLK
4th CLK
5th CLK
CLK
ADV#
Address 1 Latched
Valid Address
A18-A0
Three CLK Delay
DQ31
-
DQ0
DQ0
D0
D1
D0
D2
D3
D2
D4
D3
Four CLK Delay
DQ31
-
D1
D0
Five CLK Delay
D1
D2
DQ31
-
DQ0
Figure 3. Initial Burst Delay Control
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
20
Am29BDD160G
April 8, 2003
SPANSION [ SPANSION ]
