A D V A N C E I N F O R M A T I O N
ister is accessed by the Configuration Register Read
Burst CLK Edge Data Delivery
and the Configuration Register Write commands. The
Configuration Register does not occupy any address-
able memory location, but rather, is accessed by the
Configuration Register commands. The Configuration
Register is readable any time, however, writing the
Configuration Register is restricted to times when the
Embedded Algorithm™ is not active. If the user at-
tempts to write the Configuration Register while the
Embedded Algorithm™ is active, the write operation is
ignored and the contents of the Configuration Register
remain unchanged.
The Am29BDD160 is capable of delivering data on ei-
ther the rising or falling edge of CLK. To deliver data
on the rising edge of CLK, bit 6 in the Control Register
(CR6) is set to 1. To deliver data on the falling edge of
CLK, bit 6 in the Control Register is cleared to 0. The
default configuration is set to the rising edge.
Burst Data Hold Control
The device is capable of holding data for either one or
two CLKs, depending upon the state of bit 9 in the
Control Register (CR9). If bit 9 of the Control Register
is cleared, data on DQ0–DQ31 (when WORD# = VIH)
is held for one CLK. If bit 9 is set to a 1, then data is
held for two CLK cycles. The default configuration is to
hold data for one CLK.
The Configuration Register is a 16 bit data field which
is accessed by DQ15–DQ0. Data on DQ31–DQ16 is
ignored during a write operation when WORD# = VIL.
During a read operation, DQ31–DQ16 returns all ze-
roes. Table 8 shows the Configuration Register. Also,
Configuration Register reads operate the same as Au-
toselect command reads. When the command is is-
sued, the bank address is latched along with the
command. Reads operations to the bank that was
specified during the Configuration Register read com-
mand return Configuration Register contents. Read
operations to the other bank return flash memory data.
Either bank address is permitted when writing the
Configuration Register read command.
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the
burst access is immediately terminated and the device
defaults back to asynchronous read mode. Refer to
RESET#: Hardware Reset Pin for more information on
the RESET# function.
Configuration Register
The Am29BDD160 contains a Configuration Register
for configuring read accesses. The Configuration Reg-
Table 8. Configuration Register Definitions
CR13 CR12 CR11 CR10
IAD3 IAD2 IAD1 IAD0
CR15
RM
CR14
CR9
CR8
WC
Reserved
DOC
CR7
BS
CR6
CC
CR5
CR4
CR3
CR2
BL2
CR1
BL1
CR0
BL0
Reserved
Reserved
Reserved
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to “0”.
April 8, 2003
Am29BDD160G
21
SPANSION [ SPANSION ]
