A D V A N C E I N F O R M A T I O N
CE#
CLK
ADV#
A0-
A18
Address 0
Address 1
Address 2
Address 3
D0
D1
D2
D3
D3
DQ0
-
DQ31
OE#
WE#
VIH
Float
Float
VOH
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 1. Asynchronous Read Operation
when burst mode is enabled. Read operations to
these locations results in the data remaining valid
while OE# is at VIL, regardless of the number of CLK
cycles applied to the device.
Synchronous (Burst) Read Operation
The Am29BDD160 is capable of performing burst read
operations to improve total system data throughput.
The device is available in three burst modes of opera-
tion: linear and continuous sequential burst mode. 2, 4
and 8 double word (x32) and 4 and 8 word (x16) ac-
cesses are configurable as either sequential burst ac-
cesses. 16 and 32 word (x16) accesses are only
configurable as linear burst accesses. Additional op-
tions for all burst modes include initial access delay
configurations (2–16 CLKs), data hold for either 1 or 2
CLKs, and whether the data is presented on either the
rising or falling edge of the CLK signal. Device config-
uration for burst mode operation is accomplished by
writing the Configuration Register with the desired
burst configuration information. Once the Configura-
tion Register is written to enable burst mode opera-
tion, all subsequent reads from the array are returned
using the burst mode protocols. Like the main memory
access, the SecSi Sector memory is accessed with
the same burst or asynchronous timing as defined in
the Configuration Register. However, the user must
recognize that continuous burst operations past the
256 byte SecSi boundary returns invalid data.
Linear Burst Read Operations
Linear burst read mode reads either 4, 8, 16, or 32
words (1 word = 16 bits), depending upon the Configu-
ration Register option. If the device is configured with
a 32 bit interface (WORD# = VIH), the burst access is
comprised of 4 clocked reads for 8 words and 16
clocked reads for 32 words (See Table 5 for all valid
burst output sequences). The number of clocked
reads is doubled when the device is configured in the
16-bit data bus mode (WORD# = VIL). The IND/WAIT#
pin transitions active (VIL) during the last transfer of
data during a linear burst read before a wrap around,
indicating that the system should initiate another
ADV# to start the next burst access. If the system con-
tinues to clock the device, the next access wraps
around to the starting address of the previous burst
access. The IND/WAIT# signal remains inactive (float-
ing) when not active. See Table 5 for a complete 32
and 16 bit data bus interface order. 16 and 32 word
options are restricted to sequential burst accesses,
only.
Burst read operations occur only to the main flash
memory arrays. The Configuration Register and pro-
tection bits are treated as single cycle reads, even
16
Am29BDD160G
April 8, 2003
SPANSION [ SPANSION ]
