A D V A N C E I N F O R M A T I O N
taken to VIL prior to the end of a linear burst sequence, IND/WAIT# signal remain in the float state until OE# is
the previous address is discarded and subsequent
burst transfers are invalid until ADV# transitions to VIH
before a clock edge, which initiates a new burst se-
quence.
taken to VIL.
IND/WAIT# Operation in Linear Mode
The IND/WAIT#, or End of Burst Indicator signal
(when in linear modes), informs the system that the
last address of a burst sequence is on the DQ data
bus. For example, if a 4-word linear burst access is
enabled using a 16-bit DQ bus (WORD# = VIL), the
IND/WAIT# signal transitions active on the fourth ac-
cess. If the same scenario is used, but instead the
32-bit DQ bus is enabled, the IND/WAIT# signal transi-
tions active on the second access. The IND/WAIT#
signal has the same delay and setup timing as the DQ
pins. Also, the IND/WAIT# signal is controlled by the
OE# signal. If OE# is at VIH, the IND/WAIT# signal
floats and is not driven. If OE# is at VIL, the IND/WAIT#
signal is driven at VIH until it transitions to VIL indicating
the end of burst sequence. The IND/WAIT# signal tim-
ing and duration is controlled by WC (WAIT#), CC
(Clock Configuration), and DOC (Data Output Config-
uration) bits in the Configuration Register (See “Con-
figuration Register” for more information). The
following table lists the valid combinations of the Con-
figuration Register bits that impact the IND/WAIT# tim-
ing.
RESET# Control in Linear Mode
The RESET# pin immediately halts the linear burst ac-
cess when taken to VIL. The DQ data bus and
IND/WAIT# signal float. Additionally, the Configuration
Register contents are reset back to the default condi-
tion where the device is placed in asynchronous ac-
cess mode.
OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the lin-
ear burst data on the DQ data bus and the IND/WAIT#
pin. De-asserting the OE# pin to VIH during a burst op-
eration floats the data bus and the IND/WAIT# pin.
However, the device will continue to operate internally
as if the burst sequence continues until the linear burst
is complete. The OE# pin does not halt the burst se-
quence, this is accomplished by either taking CE# to
V
IH or re-issuing a new ADV# pulse. The DQ bus and
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Am29BDD160G
April 8, 2003
SPANSION [ SPANSION ]
