A D V A N C E I N F O R M A T I O N
Table 6. Valid Configuration Register Bit Definition for IND/WAIT#
DOC
WC
0
CC Definition
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on falling CLK edge
IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on falling CLK edge
IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
IND/WAIT# = VIL for 2-CLK cycles, Active on last transfer, Driven on falling CLK edge
IND/WAIT# = VIL for 2-CLK cycles, Active on last transfer, Driven on rising CLK edge
IND/WAIT# = VIL for 2-CLK cycles, Active on second to last transfer, Driven on falling CLK edge
IND/WAIT# = VIL for 2-CLK cycles, Active on second to last transfer, Driven on rising CLK edge
0
1
1
0
0
1
1
CE#
CLK
3 Clock Delay
ADV#
Address 1 Latched
A0-A18
Address 1
Address 2
Invalid
D1
D2
D3
D0
OE#
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. For a 16-bit data bus, A-1 is required. Figure shown with 3-CLK initial access
delay configuration, linear address, 4-doubleword burst, output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted
on the last transfer before wrap-around.
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
April 8, 2003
Am29BDD160G
19
SPANSION [ SPANSION ]
