CXD1968AR
FEC_STATUS
Read Only
Offset Address: 0x84
Bit
Name
Description
Default R/W
1: When a severely errored second is detected, i.e. when n or
more 204-byte packets are uncorrectable in a second. n is
defined by the LT_QLTY_THRESHOLD register.
7
Ber_ses
—
—
—
R
R
R
1: When 1 or more 204-byte packets are uncorrectable in a
second. (Note: An uncorrectable error occurs when more
than 8 error bytes are present in a single packet.)
6
5
Ber_es
1: When FEC locked. When n SYNC bytes have been
detected (n is programmable and defined by the
SET_SYNC_DETECT register).
Lck_Flag
1: When transport stream lock lost condition detected. This
occurs when n SYNC bytes go undetected (n is
programmable and defined by the SET_SYNC_DETECT
register).
4
Ts_Llck_Flag
—
R
1: When transport stream lock condition detected. Valid
MPEG2 data is generated by the device from this time.
3
2
Ts_Synch_Lock
Vtb_Sync
—
—
R
R
1: When viterbi synchronization condition detected. Viterbi
synchronization operation controlled by VIT_SN and
VIT_ST registers.
1: When new bit error rate value is available. This bit is cleared
by a register read operation.
1
0
New_Ber_es
Reserved
—
—
R
R
SET_SYNC_DETECT
Read/Write
Description
RESET: 0xD6
Default R/W
Offset Address: 0x86
Bit
Name
Controls whether the pre-RS decoder sync detect
count is decremented or reset when a missing sync
byte is detected while locking.
7
Synch_Cntr_Mode
1
1
R/W
R/W
0: Reset
1: Decrement
Controls whether the post-RS decoder sync detect
count is decremented or reset when a missing sync
byte is detected.
6
Ts_Synch_Cntr_Mode
0: Reset
1: Decrement
Sync byte counter threshold at which lock is lost
(post-RS decoder only).
5:3 Sync_Loss_Lddr_Length[2:0]
2:0 Synch_Lddr_Lngth[2:0]
010
110
Sync byte counter threshold at which lock is
achieved (pre- and post-RS decoder).
R/W
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SONY [ SONY CORPORATION ]
