CXD1968AR
TPS_RESERVED_2_EVEN
Read Only
Offset Address: 0x7C
Bit
Name
Description
Default
Bit
R
7:6 Reserved
Not used
—
TPS reserved bit S48 – DVB-H time sliced data present
in received data. In hierarchical mode, these bits
correspond to LP stream.
5
4
TimeSlicedData
MPE-FECData
—
R
TPS reserved bit S49 – DVB-H MPE-FEC encoded
data present in received data. In hierarchical mode,
these bits correspond to LP stream.
—
—
R
R
TPS reserved bits S50-S53 received during TPS frame
numbers 2 and 4.
3:0 TPS_RESERVED_EVEN
DCC_OFFSET_I
Read Only
Offset Address: 0x7D
Bit
Name
Description
Default R/W
7:0 DCC_OFFSET_I
Detected DC offset value on the I channel (signed)
—
R
DCC_OFFSET_Q
Read Only
Offset Address: 0x7E
Bit
Name
Description
Default R/W
7:0 DCC_OFFSET_Q
Detected DC offset value on the Q channel (signed)
—
R
DCC_MISC
Read/Write
Description
RESET: 0x03
Offset Address: 0x7F
Bit
Name
Default R/W
00000 R/W
7:3 RESERVED
Sets the DCC gain value as indicated in the table below:
Register value 2K Mode 8K Mode
0
1
2
3
2–16
2–17
2–18
2–19
2–18
2–19
2–20
2–21
2:1 DCC_GAIN
01
1
R/W
R/W
If set, DC offset cancellation is enabled. This bit should be set
when using DC-coupled ZIF tuners.
0
DCC_ENABLE
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SONY [ SONY CORPORATION ]
