CXD1968AR
FEC Registers
FEC_PARAMS
Read/Write
RESET: 0x1A
fec_param reset
Default R/W
Offset Address: 0x80
Bit
Name
Description
If the TSCLK output is gated (bit Tsclk_full of BBPARAMS low)
and TS smoothing enabled (bit ENABLE of SMOOTH_CTRL
high), then setting this bit ensures that the TSCLK output
remains active during any gap in the TS output.
7
Tsclk_cont
0
R/W
0: TSCLK inactive during gaps
1: TSCLK active during gaps
Auto clearing of Interrupt flag.
0: Auto clear disabled
6
5
Auto_clear
0
0
R/W
R/W
1: Auto clear enabled
When the transport stream is operating in its serial mode (see
bit 4 below) this bit controls on which TSDATA bit the serial
data is presented.
Ser_data_on_msb
0: Data is presented on TSDATA[0]
1: Data is presented on TSDATA[7]
Determines whether the parallel or serial interface for the
transport stream is selected.
0: Serial interface selected
1: Parallel interface selected
4
TS_parallel_sel
1
R/W
When serial interface selected, Pins TSDATA[7] or TSDATA[0]
(see bit 5 above) drive the serial data.
Selects whether the most significant bit of a byte is presented
on TSDATA bit[7] or bit[0]. In serial mode this bit selects
whether the most significant bit is presented as the first or last
bit of a byte.
3
2
Output_Sel_Msb
Measurement_Sel
1
0
R/W
R/W
0: MSB is TSDATA[0] (last bit, serial mode).
1: MSB is TSDATA[7] (first bit, serial mode).
Selects BER Measurement or Estimation.
0: Estimation
1: Measurement
When Measurement is selected, the RS_DISABLE bit must
also be set to enable BER measurement to be made.
Tri-states transport stream outputs (serial and parallel).
1
0
Tri_State_Outputs
RS_Disable
1
0
R/W
R/W
0: Outputs driven
1: Outputs tri-state
Enables/Disables RS decoder.
0: Enables error correction
1: Passes data without correction
- 82 -
SONY [ SONY CORPORATION ]
