CXD1968AR
Channel Correction (CHC)
This block uses the estimated channel frequency response to equalize the carriers against frequency
selective attenuation in the channel.
TPS Cell Decode and Frame Synchronization (TPS)
The Transmission Parameter Signaling (TPS) pilots convey information used to configure the receiver and
delimit the COFDM frame boundaries. This block decodes the TPS pilot carriers and generates frame
synchronization signals. All the TPS information (shown below) is readable via I2C registers.
Length indicator – Needed to read Cell-ID and reserved TPS bits
Frame number within superframe (0-3)
Constellation (QPSK, 16QAM, 64QAM)
Hierarchy information (non-hierarchical, α = 1, α = 2, α = 4)
High priority stream code rates (1/2, 2/3, 3/4, 5/6, 7/8)
Low priority stream code rates (1/2, 2/3, 3/4, 5/6, 7/8)
Guard interval (1/32, 1/16, 1/8, 1/4)
Transmission mode (2K, 8K)
All TPS bits reserved for future use (S40-S53), such as Cell ID and DVB-H indicator bits
Symbol Deinterleaver (SDI)
The transmitter interleaves the QAM symbols to ensure that a given QAM symbol is mapped to a different
carrier in each COFDM symbol, to avoid a succession of errors at the Viterbi decoder input due to
frequency selective attenuation involving several adjacent carriers. The symbol deinterleaver deinterleaves
the corrected carriers from the channel estimation and correction blocks together with the reliability
information.
Symbol Demapper (DMP)
The demapper processes the complex symbols and reliability information issued from the symbol
deinterleaver, generating weighted soft decision information for each bit.
Bit Deinterleaver (BDI)
Depending upon the QAM level used, the transmitter splits up the input data bits into 2, 4 or 6 streams
which are then interleaved to ensure that consecutive input data bits are not mapped to the same QAM
symbol. The bit deinterleaver reverses this process by deinterleaving the soft decision information for each
bit from the Symbol Demapper. In hierarchical mode, this block outputs a high priority and low priority bit
stream. In non-hierarchical mode, a single bit stream is output.
Low/High Priority Stream Select
For hierarchical transmissions, this block selects (via an I2C register) either the high priority or low priority
transport stream for processing by the remainder of the decoder as shown in Fig. 2.
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SONY [ SONY CORPORATION ]
