CXD1968AR
Forward Error Corrector (FEC)
BER Figures
Lost Lock Flag
LOCK Flag
Transport Stream
Lock Detection &
ISYNC Detect
SYNC Byte Lock
Detection
BER
Measurement
FEC Register Bank
(FRB)
Inverted
SYNC Flag
Bits from
High/Low
Priority
Select
Reed-
Solomon
Decoder
Energy
Dispersal
Removal
Viterbi
Decoder
Byte
Deinterleaver
Baseband Transport
Interface Stream Data
BB0
BB1
BB2
BB3
SYNC
Flag
SYNC
Flag
SYNC
Flag
SYNC
Flag
Fig. 2. FEC Block Diagram (Viterbi decoder to transport stream output only)
Viterbi Decoder (VIT)
The Viterbi decoder uses the weighted soft decision data to perform a maximum likelihood estimation of each
received bit. All code rates in the ETSI (EN) 300 744 standard are supported. Bit error rates at the input and
output of this decoder can be monitored via the I2C bus. The serial bit stream output of the decoder is
converted into byte wide format by a serial to parallel converter before it is passed to the byte deinterleaver.
Sync Byte Lock Detection
This block detects the MPEG2-TS sync bytes or inverted sync bytes at the output of the Viterbi decoder in
order to ensure correct synchronization of the byte deinterleaving and correct identification of the inverted
sync bytes.
Byte Deinterleaver
This block implements standard DVB compatible Forney type convolutional deinterleaving (I = 12, N = 204,
M = 17, where M = N/I). Burst errors are split up across multiple MPEG2-TS packets, which increases the
probability of successful Reed-Solomon error correction.
Reed-Solomon Decoder
This block is a DVB compatible (255,239) Reed-Solomon decoder implementing the standard DVB shortened
(204,188) code using a (GF generation polynomial p(x) = x8 + x4 + x3 + x2 + 1) to correct up to t = 8 erroneous
bytes per MPEG2-TS packet. R/S decoding errors occurring when more than 8 bytes are in error are used to
calculate error statistics, and are also signaled on the MPEG2-TS interface TSERR signal.
Transport Stream Lock Detection and Sync Byte Inversion
This block detects the MPEG2-TS sync bytes and inverted sync bytes after correction by the R/S decoder
in order to provide a more resilient lock detection mechanism which is called Transport Stream Lock in this
document. Operation is similar to the sync byte lock detection block described above. This block also
detects the inverted sync bytes, which are then inverted by the energy dispersal block.
Energy Dispersal
The error-corrected bytes are derandomized with a 15-stage PRBS (Pseudo Random Binary Sequence)
generator, with polynomial 1 + X14 + X15 and start-up sequence “100101010000000”. Sync bytes are not
derandomized, and when an inverted sync byte is detected, every 8th packet, the PRBS resets to the
start-up sequence and the sync byte is reinverted. The derandomized data is output through the TSDATA
pins, along with a data clock and synchronization signal.
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SONY [ SONY CORPORATION ]
