CXD1968AR
Symbol Resampling (ITP)
This block resamples the complex baseband data to compensate for errors between the transmitter clock
and ADC sampling clock frequency thus ensuring the FFT block receives the correct number of samples
per OFDM symbol. An all-digital resampling technique is used which eliminates the cost and stability issues
associated with internal or external VCXOs. The timing offset can be read from an I2C register allowing
external monitoring or control.
Frequency Synchronization Loop (CRL)
The frequency synchronization loop compensates for intentional transmitter carrier frequency offsets and
tuner local oscillator frequency error inherent in the RF to IF conversion process. An all-digital AFC
technique estimates the frequency shift using the pilots in the OFDM signal and derotates the I/Q
constellation before the FFT process. Frequency offset information can be read from an I2C register.
This information may be extracted during a channel scan and subsequently applied to the tuning when
pre-selecting (zapping) a channel. The offset range can be programed to allow faster acquisition to
broadcast channels even beyond 3 × ±166kHz transmitter offset. Scanning under software control is
simplified using the extended acquisition range.
ACI and CCI Rejection and Digital AGC (CSF + CAS)
These blocks filter any residual adjacent channel interference such as NICAM energy leaking through the
edges of the SAW filter. The CCI filter can optionally cancel co-channel interference such as vision carrier
of an analog TV signal. Digital AGC is also performed to restore a consistent signal after filtering. The CCI
filter is automatically applied in the presence of analog co-channel interference, resulting in optimum
performance for the received channel. The CSF block provides extra adjacent channel rejection,
particularly in ZIF mode where there is reduced folding in-band of ACI signals.
COFDM Symbol Synchronization Block (SYR)
This block acquires and tracks the position of the FFT sampling window within the OFDM symbol, to allow
the FFT to recover the useful carriers including pilot tones with minimal ISI. This block can be programed
to perform a fast detection of the guard time interval and mode without using TPS, reducing acquisition
time. Alternatively a specific mode and guard configuration can be programed also reducing acquisition
times for known channels.
The CXD1968AR utilizes a new tracking algorithm which improves symbol tracking in multipath channels,
particularly beneficial for reception of SFN broadcasts where there can be echoes outside the guard
interval. The algorithm permits acquisition and tracking of pre-cursive and post-cursive echo delays inside
and outside the guard interval, and also automatically tracks the “birth” and “death” of echoes occurring at
different delays, even if the delay of the main echo path changes. The tracker contains automatic CCI
detection and filter selection further optimizing channel reception.
FFT Processor
This block performs a 2048 or 8192 point FFT on the derotated I/Q samples.
Pilot Processing and Common Phase Error (CPE) Correction (SCR and PPM)
This block corrects for the phase slope and common phase error present on the carriers due to the FFT
trigger point being chosen to minimize ISI. A fast acquisition mode can be programed to allow the device
to start outputting transport stream data before a full superframe has been received.
Channel Estimation
This block estimates a time varying channel frequency response using the pilot carriers embedded in every
COFDM symbol. This estimate is then interpolated in the frequency domain and used to correct each of
the individual OFDM carriers in the CHC block. This block also estimates the signal and noise power for
each carrier, which is used as a reliability estimate to weight the soft decisions of each bit fed to the Viterbi
decoder. This feature helps to improve PAL CCI performance where vision and sound carriers can distort
nearby COFDM carriers.
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SONY [ SONY CORPORATION ]
