CXD1968AR
2. Functional Description
The block diagram of the CXD1968AR is shown in Fig. 1.
Improvements over CXD1976R and CXD1973Q
The CXD1968AR incorporates some enhanced functionality over the CXD1976R. The following improvements
offer performance benefits, system cost savings and simplify control of the device:
1. Auto-recovery/acquisition controller
This easy to use hardware controller eliminates the processing load on the host processor software during
acquisition and will reacquire the channel if the transport stream is lost. The demodulator registers are
initialized by host software after power up/reset, then the controller is enabled. The controller automatically
acquires the channel selected by the tuner, and continuously monitors for loss of TS or TPS lock and reacquires
the channel if necessary. This functionality also reduces host software overhead for zapping, as the host
processor need only write a new channel frequency to the tuner – the demodulator will automatically
acquire the new channel. The controller can also reduce host processor overhead during channel
scanning. Conventional host control of the demodulator is also possible by disabling the controller.
2. Operation from a low cost tuner crystal reference
The CXD1968AR can be clocked from a standard 20.48MHz crystal (as in the CXD1976R) or from a tuner
generated clock output, typically 4MHz, but can be in the range 4MHz to 20MHz by suitable programming
of the PLL registers.
3. Impulse noise cancellation
This block compensates for the effects of impulse noise detected in the incoming signal using a proprietary
algorithm.
4. Zero IF tuner interface
The CXD1968AR includes an optional Zero IF tuner interface to allow use of low cost silicon tuners. This
interface includes several new blocks to handle typical signal impairments caused by the Zero IF tuning
process:
I/Q amplitude imbalance correction (AGC)
Mismatches in the I and Q tuner signal paths can cause distortion of the I/Q signal. Dual AGC power
estimation blocks individually monitor the I and Q input channels after the ADCs, and drive dual AGC
amplifier PWM control outputs, allowing independent control of I and Q channel amplitudes in the tuner
baseband amplifiers. The AGC gains of the I and Q channels can be read via I2C.
I/Q phase quadrature imbalance correction (QIC)
Mismatches in the I/Q quadrature in the tuner local oscillator and signal paths can cause a uniform
phase distortion of the I/Q signal across the band. This type of frequency independent I/Q phase
imbalance can be corrected by this block. The detected I/Q phase imbalance can be read via I2C.
DC offset correction
DC offsets in the input signal are estimated and removed by this block. The detected DC offset can be
read via I2C.
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SONY [ SONY CORPORATION ]
