CXD1968AR
JTAG
The JTAG facility can be utilized, but refer to section 2 of this datasheet for information on how to configure
the connections.
It may be necessary to apply pull-down resistors to these pins:
TCK
Pin 29
TRSTN Pin 34
Power Supply Sequencing
During the power-up sequence of the 1.2V and 3.3V supplies, it is important to ensure that the 1.2V supply
is not applied before the 3.3V supply. Failure to do this could result in latch up and the CXD1968AR will
not function correctly.
During power-down the 3.3V supply should not fall below the 1.2V supply, as both decay.
Both conditions can be met by deriving the 1.2V supply from the 3.3V supply.
If this configuration is not utilized or the timing cannot be guaranteed, it is possible to prevent supply latch-
up by adding a Schottcky diode between the supplies. Connect the diode with anode to 1.2V supply and
cathode to 3.3V supply. This is only appropriate when both analog and digital 3.3V supplies are derived
from the same regulator. The diode used must be a Schottcky type for low forward voltage drop, ie. 0.4V
or less. This solution is applicable to both power-up and power-down conditions.
Reset
Note the hardware reset requirements outlined in section 3. As has been stated, when the CXD1968AR is
powered up, it must be hard reset. This can be achieved simply by using an external RC circuit with time
constant of around 1ms, values of 10kΩ and 100nF are employed in the recommended application.
Alternatively this function may be provided by a specific device or host controller and the timing will be
dependant upon supply rise time.
Pull-ups
The following pins should be used with pull-up resistors:
SDA
SCL
QSDA
QSCLK
Pin 26
Pin 25
Pin 63
Pin 64
INTRPTN Pin 5 (if used)
A nominal value of 10kΩ is used with the CXD1968AR but other values are permissible dependant upon
the interface requirement. The maximum loading is stated in the DC Electrical Characteristics, a value of
less than 1000Ω is not advisable.
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SONY [ SONY CORPORATION ]
