CXD1968AR
Interrupts
These can be used to quickly ascertain the status of the chip. This can be done in one of two ways:
1. Regularly polling the interrupt flags over the I2C bus.
2. Using the INT pin to raise a hardware interrupt, then getting the host controller to read the interrupt flags
to determine the type of interrupt.
The interrupts are of two basic types:
1. High-level interrupts: the flags for these are contained in the interrupt status register
(INTERRUPT_SOURCE).
2. OFDM core interrupts: the flags for these are contained in the core interrupt status register
(COR_INTSTAT).
High-level Interrupts
These interrupts relate to the key stages in acquiring transport stream lock. Interrupt flags are available
for the following events:
0. COFDM demodulator interrupt (poll the COR_INTSTAT register to find out why)
1. Transport stream lock
2. Transport stream lost lock
3. Reserved
4. Errored second detected
5. Severely errored second detected
6. Codeword rejected (>8 errors in current packet)
7. Transport stream smoothing under/over flow
To clear each interrupt, write a “1” to the corresponding bit in the INTERRUPT_SOURCE register after
the interrupt has occurred.
COFDM Demodulator Interrupts
COFDM demodulator interrupt flags are available for the following events:
0. AGC lock change (AGC gained lock/AGC lost lock)
1. End of symbol (from Symbol Recovery block)
2. FFT done: FFT processing complete on current symbol
3. Receipt of a TPS block
4. Change of TPS parameters
5. TPS block has a bad BCH checksum.
Enabling Core Interrupts
Interrupts are enabled using the COR_INTEN register. To enable any core interrupt, the INTEN Global
bit in the COR_INTEN register must be set. Each individual interrupt is then enabled by setting the
appropriate bit in the COR_INTEN register.
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