CXD1968AR
4. Application Circuit
GND
C16
33pF
C35
33pF
Y2
20.480MHz
R5
100
R6 2.2M
1.2V-AD
1.2V-D
3.3V-D 1.2V-D
3.3V-D
GND
R1 10k
R2 10k
GND
GNDGND
GNDGND
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND
49
50
51
52
32
31
30
29
AINP_Q
AINM_Q
AVDD_Q
AVSS_Q
TMS
TDI
3.3V-D
3.3V-A
GND
TDO
TCLK
R13
2.2k
R14
2.2k
GND
53 GUARD_Q
CVSS 28
CVDD 27
SDA 26
SCL 25
DVDD 24
GND
54
55
1.2V-D
DAREFP
DAREFM
C31 100nF
GND
SDA
SCL
C69 1nF
56 GUARD_I
TUNER_IF_NEG
57
58
3.3V-D
GND
AINM_I
AINP_I
C71 1nF
DVSS
23
22
21
20
19
18
17
TUNER_IF_POS
GND
59 AVSS_I
60 AVDD_I
TSDATA7
TSDATA6
TSDATA5
3.3V-A
61
REFIN
62 REFOUT
TSDATA4
TSDATA3
TSDATA2
TUNER_DAT
TUNER_CLK
63 TUNERDAT
64 TUNERCLK
R19
10k
R20
10k
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
5V-A
R23 1.0k
TUNER_IF_AGC
C33
470nF
GND
3.3V-D
GND
1.2V-D
GND
1.2V-D
GND
Mount components
close to Pin 2
TSData[0:7]
3V-VCC
TSCLK
TSVALID
TSSYNC
TSERROR
R16
10k
R17
10k
Power supply decoupling.
All supply pins to be decoupled
with 100nF ceramic capacitors.
(not shown)
RESETN
INTRPTN
C36
100nF
GND
Note) For High IF or Low IF mode, use PIN 57, 58 (AINM_I, AINP_I) as the ADC input.
And, PIN 49, 50, which are unused, should be kept open.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Fig. 5. Application and Test Measurement Schematic for IF Mode of Operation
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SONY [ SONY CORPORATION ]
