CXD1968AR
5. Design Guidelines
This section describes the application of the CXD1968AR DVB-T COFDM demodulator IC.
The schematic contained within the previous section should be used to assist with following descriptions.
Refer to the separate engineering application notes for additional information about specific configurations and
uses. EAN-0065 is intended to assist users familiar with the CXD1976R in making the transition to the
CXD1968AR.
Circuit Configurations
The CXD1968AR has the capability to operate with High IF, Low IF and Zero IF conventional or silicon tuners.
The application described in this section is for a conventional High IF tuner.
ADC Input
The ADC input of the CXD1968AR is directly compatible with differential sources. Where the tuner can supply
only a single-ended IF signal, a balun is recommended to maximize the dynamic range of the IF strip.
The ADC input has a high impedance input (> 1kΩ). The tuner output impedance is normally low (< 100Ω)
and it is not necessary to match to the ADC. The differential inputs are self-biasing and our
recommendation is to AC couple the input signals with 1nF or larger capacitors.
Note) For High IF or Low IF mode, use PIN 57, 58 (AINM_I, AINP_I) as the ADC input.
ADC Reference Components
The ADC reference voltage at Pins 61 and 62 (connected together) should be decoupled with 100nF
multilayer capacitor for optimum performance.
AGC
The CXD1968AR generates an IF AGC output. This signal is a digital PWM format requiring an integrating
RC filter to provide a variable DC control voltage for the tuner or IF circuit.
A second AGC output can be generated for RF gain control. The output signal is also PWM format, but may
be configured as a fixed logic level output for general-purpose control functions. When used as an AGC
output, an integrating RC filter is required. This pin may alternatively be used as a logic input at a nominal
3.3V but is 5V compliant.
The application values for the PWM integrating filter of 1000Ω and 470nF are chosen to give a 0.5ms time
constant which approximates to a 400Hz cutoff frequency. For the IF AGC loop, this value is chosen as a
compromise between suppressing the PWM high-frequency components and permitting the AGC loop to
track 50/60Hz AM interference which may be present on the received signal. Typically the AGC response
time to a step input, as might occur changing channel, is 20ms. If the filter values are modified perhaps to
achieve faster channel acquisition, then note the possible impact on AM rejection.
Clock and Crystal Oscillator
The oscillator cell will operate with an external crystal or use an external clock, this is configured at start-
up by register settings described in the application note EAN-0066. If using an external clock, this must be
present before programming can be applied.
Performance with an external clock may be compromised if the quality of the reference signal is poor.
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