CXD1199AQ
2-2-12. HADRC-M (host address counter-middle) register
This counter keeps the addresses which write or read the data with host into/from the buffer. If sound map
data is to be transferred before the data is transferred (immediately after the host has set the BFRD and
BFWR bits (bits 7 and 6) of the HCHPCTL register high), 600CHEX, 6A0CHEX or 740CHEX (1MRAM is low)
is loaded into HADRC. At any other time, the HADR (sub CPU register) value is loaded.
When data from the host is written into the buffer or data to the host is read from the buffer, the HADRC
value is output from MA0 to 16. HADRC is incremented each time one byte of data from the drive is read
from the buffer (BFRD is high) or written into the buffer (BFWR is high).
The MSB (bit 16) of HADRC is read out from bit 4 of the HXFRC-H register.
2-2-13. DADRC-L (drive address counter-low) register
2-2-14. DADRC-M (drive address counter-middle) register
The MSB (bit 16) of DADRC is read out from bit 5 of the HXFRC-H register.
2-2-15. HIFSTS (host interface status) register
bit 7 : BUSYSTS (busy status)
This has the same value as BUSYSTS (bit 7) of the host HSTS register. It is set high when the
host writes a command into the command register and low when the sub CPU sets CLRBUSY of
the CLRCTL register.
bit 6 : RSLWRDY (result write ready)
The result register is not full when this bit is high. The sub CPU can write the result of the
command execution into this register.
bit 5 : RSLEMPT (result empty)
The result register is empty when this bit is high. It indicates that all the status sent from the sub
CPU to the host (result register) have been read out by the host.
bit 4 : PRMRRDY (parameter read ready)
The HSTPRM register is not empty when this bit is high. The sub CPU can read out the command
parameters from the HSTPRM register.
bit 3 : DMABUSY (DMA busy)
This is high when data is being transferred between the buffer memory and the host.
It is high when the host sets BFRD (bit 7) or BFWR (bit 6) of the HCHPCTL register high. It is low
in the case below:
• When the data transfer FIFO (WRDATA, RDDATA registers) is empty after the level of HXFRC
has dropped to 00HEX.
bit 2 : HINTSTS#2 (host interrupt status #2)
This is high when the sub CPU writes data into HINT#2 (HIFCTL register bit 2) and low when the
host writes “high” into CLRINT#2 (HCLRCTL register bit 2). It is used to monitor interrupts for the
host.
bit 1 : HINTSTS#1 (host interrupt status #1)
This is high when the sub CPU writes data into HINT#1 (HIFCTL register bit 1) and low when the
host writes “high” into CLRINT#1 (HCLRCTL register bit 1). It is used to monitor interrupts for the
host.
bit 0 : HINTSTS#0 (host interrupt status #0)
This is high when the sub CPU writes data into HINT#0 (HIFCTL register bit 0) and low when the
host writes “high” into CLRINT#0 (HCLRCTL register bit 0). It is used to monitor interrupts for the
host.
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