CXD1199AQ
3. Host Registers
3-1. Write registers
3-1-1. ADDRESS register
bits 7 to 2 : Reserved
Normally set low.
bits 1, 0 : RA1, 0
These are the address expansion bits. The host read/write register is selected according to the
combination of these bits with the HA1 and 0 inputs. Refer to the table at the end of this section for
the register selection methods.
3-1-2. COMMAND register
This is the register in which the host writes the commands. When the host writes a command in it, an
interrupt request can be output to the sub CPU. The control program specifies bit allocation and functions.
3-1-3. PARAMETER register
The host writes the command parameters required to execute commands in this register. The register has
an 8-byte FIFO configuration.
3-1-4. HCHPCTL (host chip control) register
bit 7 : BFRD (buffer read)
The transfer of (drive) data from the buffer memory to the host is started by setting this bit high.
The bit is automatically set low upon completion of the transfer.
bit 6 : BFWR (buffer write)
The transfer of data from the host to the buffer memory is started by setting this bit high. The bit is
automatically set low upon completion of the transfer.
bit 5 : SMEN (sound map En)
This is set high to perform sound map ADPCM playback.
3-1-5. WRDATA (write data) register
This is the register for writing the data to the buffer memory from the host. Data can be written in the I/O
mode or using DMAC. The register has a 2-byte FIFO configuration.
3-1-6. HINTMSK (HOST interrupt mask) register
Setting each bit in this register high enables an interrupt request from the IC to the host depending on the
corresponding interrupt status. The value of each bit has no effect on the corresponding interrupt status.
bit 7 : Reserved
bit 4 : ENBFWRDY (enable buffer write ready interrupt)
bit 3 : ENBFEMPT (enable buffer write empty interrupt)
bits 2 to 0 : ENINT#2 to 0 (enable interrupt #2 to 0)
—35—
SONY [ SONY CORPORATION ]
