CXD1199AQ
2-2-16. HSTPRM (host parameter) register
The command parameters from the host are read out from this register. The register has an 8-byte FIFO
configuration.
2-2-17. HSTCMD (host command) register
The command from the host are read out from this register.
bit6
bit5
BCK RED
PRTY CTL
SPE CTL
MODE SEL
bit5
bit1
“L”
bit0
“L”
REG
DRVIF
ADR
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
bit7
bit4
bit3
bit2
C2PO L 1st LCH LOW
BCK MD1 BCK MD0
LSB 1st
“L”
“L”
XSLOW
“L”
RAM SZ1 RAM SZ0 9 bit RAM
SPM CTL
FORM SEL AUTO DIST DEC MD2 DEC MD1
CLK DIS
HCLK DIS
“L”
CONFIG 1
CONFIG 2
DECCTL
DLADR-L
DLADR-M
DLADR-H
CHPCTL
SM BF2 DAMIX EN DACO DIS
EN DLADR ECC STR
DEC MD0
bit0
bit7
bit15
“L”
bit6
bit14
“L”
bit4
bit12
“L”
bit3
bit11
“L”
bit2
bit10
“L”
bit1
bit9
“L”
bit13
bit8
“L”
bit16
“L”
SM MUTE RT MUTE
“L”
CD-DA
“L”
SW OPEN RPS TART DBL SPD
“L”
CDDA MUTE
“L”
“L”
“L”
“L”
“L”
DRV OVRN DEC TOUT
CHP RST CLR BUSY
DRV OVRN DEC TOUT
DEC INT HST CMND HCR ISD
“L”
“L”
RE SYNC
DEC INT HST CMND HCR ISD
INTMSK
CLRCTL
CLRINT
RSLT EMPT RTADP END HDMA CMP
CLR RSLT RTADP CLR
RSLT EMPT RTADP END HDMA CMP
“L”
bit7
DIS HXFRC
bit7
bit6
“L”
bit2
bit10
bit2
bit1
bit9
bit1
bit9
bit1
bit9
“L”
bit0
bit8
bit0
bit8
bit0
bit8
bit16
“L”
HXFR-L
bit5
“L”
bit4
HADR bit16
bit4
bit3
bit11
bit3
bit11
bit3
bit11
“L”
HXFR-H
HADR-L
HADR-M
DADRC-L
DADRC-M
DADRC-H
bit6
bit5
bit13
bit5
bit13
“L”
bit15
bit7
bit14
bit6
bit10
bit2
bit12
bit4
bit15
“L”
bit14
“L”
bit10
“L”
bit12
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
“L”
HINT #2
bit2
HINT #1
bit1
“L”
HINT #0
bit0
“L”
HIFCTL
“L”
“L”
“L”
bit7
bit6
RESULT
bit5
“L”
bit4
bit3
“L”
“L”
“L”
“L”
“L”
RTADP EN
“L”
bit16
“L”
bit12
“L”
bit11
“L”
bit10
“L”
ADPMNT
RTCI
bit15
“L”
bit14
“L”
bit13
“L”
“L”
EMPHASIS
FS
“L”
S/M
“L”
BIT LNGTH
“L”
Sub CPU write registers
—33—
SONY [ SONY CORPORATION ]
