SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
MRG Timing Diagram with and without Clock Arbitration (MSPADR=0x03)
13.7.3 MSP Master Mode START Condition
To generate a START signal, user sets SEN bit (MSPM2.0). When SDA and SCL pin are both sampled High, MSP rate
generator reload MSPADR[6:0], and starts down counter. When SDA and SCL are both sampled high and MRG
overflow, SDA pin is drive low. When SCL sampled high, and SDA transmitted from High to Low is the START signal
and will set S bit (MSPSTAT.3). MRG reload again and start down counter. SEN bit will be clear automatically when
MRG overflow, the MRG is suspend leaving SDA line held low, and START condition is complete.
WCOL Status Flag
If user write to MSPBUF when START condition processing, then WCOL is set and the content of MSPBUF data is
un-changed. (the writer doesn’t occur)
START Condition Timing Diagram
13.7.4 MSP Master Mode Repeat START Condition
When MSP logic module is idle and RSEN set to 1, Repeat Start progress occurs. RSEN set and SCL pin is sampled
low, MSPADR[6:0] data reload to MSP rate generator and start down counter. The SDA pin is release to high in one
MSP rate generate counter (TMRG). When the MRG is overflow, if SDA is sampled high. SCL will be brought high. When
SCL is sampled high, MSPADR reload to MRG and start down counter. SDA and SCL must keep high in one TMRG
period. In the next TMRG period, SDA will be brought low when SCL is sampled high, then RSEN will clear automatically
by hardware and MRG will not reload, leaving SDA pin held low. Once detect SDA and SCL occur START condition,
the S bit will be set (MSPSTAT.3). MSPIRQ will not set until MRG overflow.
Note: 1. While any other event is progress, Set RSEN will take no effect.
Note:2. A bus collision during the Repeat Start condition occur:
SDA is sampled low when SCL goes from low to high.
WCOL Status Flag
If user write to MSPBUF when Repeat START condition processing, then WCOL is set and the content of MSPBUF
data is un-changed. (the writer doesn’t occur)
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