SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
SLRXCKP=1
13.6.3 Slave Transmission
After address match, the following R/W bit is set, MSPSTAT bit 2 R/W will be set. The received address will be load to
MSPBUF and ACK_ will be sent at ninth clock then SCL will be hold low. Transmission data will be load into MSPBUF
which also load to MSPSR register. The Master should monitor SCL pin signal. The slave device may hold on the
master by keep CKP low. When set. After load MSPBUF, set CKP bit, MSPBUF data will shift out on the falling edge
on SCL signal. This will ensure the SDA signal is valid on the SCL high duty.
An MSP interrupt is generated on every byte transmission. The MSPIRQ will be set on the ninth clock of SCL. Clear
MSPIRQ by software. MSPSTAT register can monitor the status of data transmission.
In Slave transmission mode, an ACK_ signal from master-receiver is latched on rising edge of ninth clock of SCL. If
ACK_ = high, transmission is complete. Slave device will reset logic and waiting another START signal. If ACK_= low,
slave must load MSPBUF which also MSPSR, and set CKP=1 to start data transmission again.
MSP Slave Transmission Timing Diagram
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