SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
Repeat Start Condition Timing Diagram
13.7.5 Acknowledge Sequence Timing
An acknowledge sequence is enabled when set ACKEN (MSPM2.4). SCL is pulled low when set ACKEN and the
content of the acknowledge data bit is present on SDA pin. If user wished to reply an acknowledge, ACKDT bit should
be cleared. If not, set ACKDT bit before starting a acknowledge sequence. SCL pin will be release (brought high) when
MSP rate generator overflow. MSP rate generator start a TMRG period down counter, when SCL is sampled high. After
this period, SCL is pulled low, and ACKEN bit is clear automatically by hardware. When next MRG overflow again,
MSP goes into idle mode.
WCOL Status Flag
If user write to MSPBUF when Acknowledge sequence processing, then WCOL bit is set and the content of MSPBUF
data is un-changed. (the writer doesn’t occur)
Acknowledge Sequence Timing Diagram
13.7.6 MSP Master Mode STOP Condition Timing
At the end of received/transmitted, a STOP signal present on SDA pin by setting the STOP bit register, PEN
(MSPM2.2). At the end of receive/transmit, SCL goes low on the failing edge of ninth clock. Master will set SDA go low,
when set PEN bit. When SDA is sampled low, MSP rate generator is reloaded and start count down to 0. When MRG
overflow, SCL pin is pull high. After one TMRG period, SDA goes High. When SDA is sampled high while SCL is high, bit
P is set. PEN bit is clear after next one TMRG period, and MSPIRQ is set.
WCOL Status Flag
If user write to MSPBUF when a STOP condition is processing, then WCOL bit is set and the content of MSPBUF data
is un-changed. (the writer doesn’t occur)
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