SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
13.7.7 Master Mode Receiving
Master receiving mode is enable by set RCEN bit.
The MRG start counting and when SCL change state from low to high, the data is shifted into MSPSR. After the falling
edge of eighth clock, the receive enable bit (RCEN) is clear automatically, the contents of MSP are load into MSPBUF,
the BF flag is set, the MSPIRQ flag is set and MRG counter is suspended from counting, holding SCL low. The MSP is
now in IDLE mode and awaiting the next operation command. When the MSPBUF data is read by Software, the BF
flag is clear automatically. By setting ACKEN bit, user can send an acknowledge bit at the end of receiving.
BF Status Flag
In Reception mode, the BF bit is set when an address or data byte is loaded into MSPBUF from MSPSR. It is cleared
automatically when MSPBUF is read.
MSPOV Flag
In receive operation, the MSPOV bit is set when another 8-bit are received into MSPSR, and the BF bit is already set
from previous reception.
WCOL Flag
If user write to MSPBUF when a receive is already progress, the WCOL bit is set and the content of MSPBUF data will
unchanged.
MSP Master Receiving Mode Timing Diagram
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Version 1.1
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