SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
13.7.6 Master Mode Transmission
Transmission a data byte, 7-bit address or the eight bit data is accomplished by simply write to MSPBUF register. This
operation will set the Buffer Full flag BF and allow MSP rate generator start counting.
After write to MSPBUF, each bit of address will be shifted out on the falling edge of SCL until 7-bit address and R/W bit
are complete. On the falling edge of eighth clock, the master will pull low SDA fort slave device respond with an
acknowledge. On the ninth clock falling edge, SDA is sampled to indicate the address already accept by slave device.
The status of the ACK bit is load into ACKSTAT status bit. Then MSPIRQ bit is set, the BF bit is clear and the MRG is
hold off until another write to the MSPBUF occurs, holding SCL low and allow SDA floating.
BF Status Flag
In transmission mode, the BF bit is set when user writes to MSPBUF and is cleared automatically when all 8 bit data
are shift out.
WCOL Flag
If user write to MSPBUF during Transmission sequence in progress, the WCOL bit is set and the content of MSPBUF
data will unchanged.
ACKSTAT Status Flag
In transmission mode, the ACKSTAT bit is cleared when the slave has sent an acknowledge (ACK_=0), and is set
when slave does not acknowledge (ACK_=1). A slave send an acknowledge when it has recognized its address
(including general call), or when the slave has properly received the data.
MSP Master Transmission Mode Timing Diagram
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