SN8F2280 Series
USB 2.0 Full-Speed 8-Bit Micro-Controller
Set PEN here
Falling edge of ninth edge
P bit is set
TMRG
PEN is clear by hardware and
MSPIRQ bit is set
SCL
SDA
P
T
MRG
TMRG
TMRG
SCL goes high on next TMRG
SDA goes low before the rising edge of SCL
to set up STOP signal
STOP condition sequence Timing Diagram
13.7.6 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeat START, STOP condition that SCL pin
allowed to float high. When SCL pin is allowed float high, the MSP rate generator (MRG) suspended from counting until
the SCL pin is actually sampled high. When SCL is sampled high, the MRG is reloaded with the content of
MSPADR[6:0], and start down counter. This ensure that SCL high time will always be at least one MRG overflow time
in the event that the clock is held low by an external device.
Clock Arbitration sequence Timing Diagram
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