6.1.3 MCU BLOCK REGISTER SUMMARY
Table 4 - MCU Block Register Summary
(These registers are external to the 8051 design core)
ADDRESS
NAME
R/W
DESCRIPTION
PAGE
RUNTIME REGISTERS
80
93
90
94
95
96
ISR_0
IMR_0
R/W
R/W
R/W
R/W
R
INT0 Source Register
19
20
20
21
21
21
INT0 Mask Register
INT1 Source Register
INT1 Mask Register
Device Revision Register
Device ID Register
ISR_1
IMR_1
DEV_REV
DEV_ID
R
UTILITY REGISTERS
97
9A
9B
C0
9C
9D
GPIO_DIR
GPIO_OUT
GPIO_IN
R/W
GPIO Direction Register
22
24
24
24
25
26
R/W
R
GPIO Data Output Register
GPIO Data Input Register
GPIO_IRQ
GPIO_MSK
UTIL_CONFIG
R/W
R/W
R/W
GPIO Interrupt Status Register (INT4)
GPIO Interrupt Mask Register (INT4)
Miscellaneous Configuration Register
SRAM Data Port Register
SRAM Address 1 Register
SRAM Address 2 Register
9F
A1
A2
SRAM_DATA
SRAM_ADD1
SRAM_ADD2
R/W
R/W
R/W
26
26
27
POWER MANAGEMENT REGISTERS
A5
A0
A6
CLOCK_SEL
WU_SRC_1
WU_MSK_1
R/W
R/W
R/W
8051 Clock Select Register
27
28
28
Wakeup Source 1 Register (INT2)
Wakeup Mask 1 Register (INT2)
SMSC DS – USB97C201
Page 16
Rev. 03/25/2002
PRELIMINARY
SMSC [ SMSC CORPORATION ]
