Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
Note 6.2 LineState: These signals reflect the current state of the Full-Speed single ended receivers.
LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current
state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1,
this is called "Single Ended One" (SE1).
An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld,
SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are
enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3]
will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts
masked to lower the suspend current as described in Section 6.3.4.
While in Low Power Mode, the Data bus is driven asynchronously because all of the transceiver clocks
are stopped during Low Power Mode.
6.3.2
Exiting Low Power Mode
To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3320 will begin
its start-up procedure. After the transceiver start-up is complete, the transceiver will start the clock on
CLKOUT and de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready
and start operating in Synchronous Mode. The transceiver will automatically set the SuspendM bit to
a 1 in the Function Control register.
T0
T1
T2
T3
T4
T5
...
CLK
LOW
POWER MODE
TURN
AROUND
DATA BUS IGNORED (SLOW LINK)
IDLE (FAST LINK)
IDLE
DATA[7:0]
DIR
Slow Link Drives Bus
Idle and STP low
Fast Link Drives Bus
Idle and STP low
STP
Note: Not to Scale
TSTART
Figure 6.10 Exiting Low Power Mode
The value for TSTART is given in Table 4.2.
Should the Link de-assert STP before DIR is de-asserted, the USB3320 will detect this as a false
resume request and return to Low Power Mode. This is detailed in section 3.9.4 of the ULPI 1.1
specification.
6.3.3
Interface Protection
ULPI protocol assumes that both the Link and transceiver will keep the ULPI data bus driven by either
the Link when DIR is low or the transceiver when DIR is high. The only exception is when DIR has
changed state and a turn around cycle occurs for 1 clock period.
In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus
to a known state while DIR is low. Two examples where this can happen is because of a slow Link
start-up or a hardware reset.
Revision 1.0 (07-14-09)
SMSC USB3320
DATA5S4HEET
SMSC [ SMSC CORPORATION ]
