Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver
Datasheet
~
~
VDDIO
CLKOUT
REFCLK
ULPI Clk Out
To PLL
Link
Reference Clk In
~
~
SMSC PHY
Clock
Source
Figure 5.2 Configuring the USB332X for ULPI Input Clock Mode (60 MHz)
ULPI Output Clock
5.4.1.2
When using ULPI Output Clock Mode, the USB3320 generates the 60MHz ULPI clock used by the
Link. The frequency of the reference clock is configured by REFSEL[2], REFSEL[1] and REFSEL[0]
as described in Table 5.10. As shown in Figure 5.3, the CLKOUT pin sources the 60MHz ULPI clock
to the Link.
~
~
ULPI Clk In
CLKOUT
REFCLK
From PLL
Link
Clock
Source
To PLL
~
~
SMSC PHY
Figure 5.3 Configuring the USB332X for ULPI Output Clock Mode
In this mode, the REFCLK pin may be driven at the reference clock frequency. Alternatively, the
internal oscillator may be used with an external crystal or resonator as shown in Figure 5.4.
An example of ULPI Output Clock Mode is shown in Figure 8.1.
SMSC USB3320
Revision 1.0 (07-14-09)
DATA2S7HEET
SMSC [ SMSC CORPORATION ]
