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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
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7.3.8 CR07  
CR07 can only be accessed in the configuration state and after the CSR has been initialized to 07H. The default  
value of this register after power up is 00H (Table 30). CR07 controls auto power management.  
Table 30 - CR07: Auto Power Management and Boot Drive Select  
BIT NO.  
BIT NAME  
Reserved  
Reserved  
Reserved  
DESCRIPTION  
Read as 0.  
Read as 0.  
Read as 0.  
0,1  
2
3
This bit controls the AUTOPOWER DOWN feature of the Parallel Port.  
4
Parallel Port  
Enable  
The function is:  
0 = Auto powerdown disabled (default)  
1 = Auto powerdown enabled  
This bit is reset to the default state by POR or a hardware reset.  
This bit controls the AUTOPOWER DOWN feature of the UART2.  
The function is:  
5
6
UART 2 Enable  
UART 1 Enable  
Reserved  
0 = Auto powerdown disabled (default)  
1 = Auto powerdown enabled  
This bit is reset to the default state by POR or a hardware reset.  
This bit controls the AUTOPOWER DOWN feature of the UART1.  
The function is:  
0 = Auto powerdown disabled (default)  
1 = Auto powerdown enabled  
This bit is reset to the default state by POR or a hardware reset.  
Read as 0.  
7
7.3.9  
CR08  
CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default  
value of this register after power up is 00H (Table 31). CR08 contains the lower 4 bits (ADRA7:4) for the ADRx  
address decoder. Bits D0 - D3 are Reserved. Reserved bits cannot be written and return 0 when read.  
Table 31 - CR08: ADRx Lower Address Decode  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
ADRA7  
ADRA6  
ADRA5  
ADRA4  
Reserved  
7.3.10 CR09  
CR09 can only be accessed in the configuration state and after the CSR has been initialized to 09H. The default  
value of this register after power up is 00H (Table 32). CR09 contains the upper 3 bits (ADRA10:8) of the ADRx  
address decoder and the ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the  
ADRx Address Decoder (Table 33).  
Table 32 - CR09: ADRx Upper Address Decoder and Configuration  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
ADRx  
Reserved  
ADRA10  
ADRA9  
ADRA8  
CONFIGURATION  
CONTROL  
SMSC DS – SP37E760  
Page 51  
Rev. 04/13/2001  
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