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SP37E760 参数 Datasheet PDF下载

SP37E760图片预览
型号: SP37E760
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 V的I / O控制器的嵌入式应用 [3.3 V I/O CONTROLLER FOR EMBEDDED APPLICATIONS]
分类和应用: 控制器
文件页数/大小: 78 页 / 507 K
品牌: SMSC [ SMSC CORPORATION ]
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7.3.1 CR00  
CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. The default  
value of this register after power up is 28H (Table 25).  
Table 25 - CR00  
BIT NO.  
BIT NAME  
Reserved  
Reserved  
Reserved  
Valid  
DESCRIPTION  
0:2  
3
4,5,6  
7
Read Only. A read returns 0  
Read Only.  
Read only. A read returns bit 5 as a 1 and bits 4 and 6 as a 0.  
A high level on this software controlled bit can be used to indicate  
that a valid configuration cycle has occurred. The control software  
must take care to set this bit at the appropriate times. Set to zero  
after power up. This bit has no effect on any other hardware in the  
chip.  
7.3.2 CR01  
CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. The default  
value of this register after power up is 9CH (Table 26).  
Table 26 - CR01  
BIT NO.  
BIT NAME  
Reserved  
DESCRIPTION  
0,1  
2
Read Only. A read returns “0”.  
Parallel Port  
A high level on this bit, supplies power to the Parallel Port (Default).  
Power1  
A low level on this bit puts the Parallel Port in low power mode.  
3
Parallel Port  
Mode  
Parallel Port Mode. A high level on this bit, sets the Parallel Port for  
Printer Mode (Default). A low level on this bit enables the Extended  
Parallel port modes. Refer to Bits 0 and 1 of CR4  
4
5,6  
7
Reserved  
Reserved  
Lock CRx  
Read Only. A read returns “1”.  
Read Only. A read returns “0”.  
A high level on this bit enables the reading and writing of CR00 -  
CR2F (Default). A low level on this bit disables the reading and  
writing of CR00 - CR2F. Note: once the Lock Crx bit is set to “0”,  
this bit can only be set to “1” by a hard reset or power-up reset.  
Note1: Power Down bits disable the respective logical device and associated pins, however the power down bit  
does not disable the selected address range for the logical device. To disable the host address registers the  
logical device’s base address must be set below 100h. Devices that are powered down but still reside at a  
valid I/O base address will participate in Plug-and-Play range checking.  
SMSC DS – SP37E760  
Page 48  
Rev. 04/13/2001  
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