7. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
5.3.3 EPP 1.7 READ
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is driven
active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The read
cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
1. The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the PData bus.
2. The host selects an EPP register and drives nIOR active.
3. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE
signal is valid.
4. If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs.
5. The Peripheral drives PData bus valid.
6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of
the cycle.
7. When the host deasserts nI0R the chip deasserts nDATASTB or nADDRSTRB.
8. Peripheral tri-states the PData bus.
9. Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
Table 15 - EPP Pin Descriptions
EPP
SIGNAL
nWRITE
PD<0:7>
INTR
EPP NAME
nWrite
Address/Data
Interrupt
TYPE
DESCRIPTION
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
O
I/O
I
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
WAIT
nWait
I
This signal is active low.
It is driven inactive as a positive
acknowledgment from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
DATASTB nData Strobe
RESET nReset
O
O
O
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device is
reset to its initial operational mode.
ADDRSTB nAddress
Strobe
This signal is active low. It is used to denote address read or
write operation.
PE
SLCT
Paper End
I
I
Same as SPP mode.
Same as SPP mode.
Printer
Selected
Status
NERR
PDIR
Error
I
O
Same as SPP mode.
Parallel Port
This output shows the direction of the data transfer on the
parallel port bus. A low means an output/write condition and a
high means an input/read condition. This signal is normally a low
(output/write) unless PCD of the control register is set or if an
EPP read cycle is in progress.
Direction
Note 1: SPP and EPP can use 1 common register.
Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct
EPP read cycles, PCD is required to be a low.
SMSC DS – SP37E760
Page 32
Rev. 04/13/2001
SMSC [ SMSC CORPORATION ]
