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LPC47M182-NR 参数 Datasheet PDF下载

LPC47M182-NR图片预览
型号: LPC47M182-NR
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的I / O控制器,主板胶合逻辑 [ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC]
分类和应用: 控制器
文件页数/大小: 223 页 / 1215 K
品牌: SMSC [ SMSC CORPORATION ]
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Advanced I/O Controller with Motherboard GLUE Logic  
Datasheet  
7.3  
Parallel Port  
The LPC47M182 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2  
type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities  
Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power  
down, changing the base address of the parallel port, and selecting the mode of operation.  
The Parallel Port configuration registers are summarized in Table 11.1 in Chapter 11 Configuration. The  
Parallel Port logical device configuration registers (0xF0 and 0xF1) are defined in Table 11.11.  
The parallel port also incorporates SMSC’s ChiProtect circuitry, which prevents possible damage to the  
parallel port due to printer power-up.  
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their  
associated registers and control gating. The control and data port are read/write by the CPU, the status  
port is read/write in the EPP mode. The address map of the Parallel Port is shown below:  
DATA PORT  
BASE ADDRESS + 00H  
BASE ADDRESS + 01H  
BASE ADDRESS + 02H  
BASE ADDRESS + 03H  
EPP DATA PORT 0 BASE ADDRESS + 04H  
EPP DATA PORT 1 BASE ADDRESS + 05H  
EPP DATA PORT 2 BASE ADDRESS + 06H  
EPP DATA PORT 3 BASE ADDRESS + 07H  
STATUS PORT  
CONTROL PORT  
EPP ADDR PORT  
The bit map of these registers is:  
D0  
PD0  
TMOUT  
D1  
PD1  
0
D2  
PD2  
0
D3  
PD3  
nERR  
D4  
PD4  
SLCT  
D5  
PD5  
PE  
D6  
PD6  
nACK nBUSY  
D7  
PD7  
NOTE  
1
1
DATA PORT  
STATUS  
PORT  
CONTROL  
PORT  
STROBE AUTOFD nINIT  
SLC  
PD3  
PD3  
PD3  
PD3  
PD3  
IRQE  
PD4  
PD4  
PD4  
PD4  
PD4  
PCD  
PD5  
PD5  
PD5  
PD5  
PD5  
0
0
1
2
2
2
2
2
EPP ADDR  
PD0  
PD0  
PD0  
PD0  
PD0  
PD1  
PD1  
PD1  
PD1  
PD1  
PD2  
PD2  
PD2  
PD2  
PD2  
PD6  
PD6  
PD6  
PD6  
PD6  
PD7  
PD7  
PD7  
PD7  
PD7  
PORT  
EPP DATA  
PORT 0  
EPP DATA  
PORT 1  
EPP DATA  
PORT 2  
EPP DATA  
PORT 3  
Note 1: These registers are available in all modes.  
Note 2: These registers are only available in EPP mode.  
SMSC LPC47M182  
95  
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)  
DATASHEET  
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