Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 37 - Register Summary for an Individual UART Channel (continued)
BIT 2
Data Bit 2
Data Bit 2
Enable
BIT 3
Data Bit 3
Data Bit 3
Enable
BIT 4
Data Bit 4
Data Bit 4
0
BIT 5
Data Bit 5
Data Bit 5
0
BIT 6
Data Bit 6
Data Bit 6
0
BIT 7
Data Bit 7
Data Bit 7
0
Receiver Line MODEM
Status
Status
Interrupt
(ELSI)
Interrupt
(EMSI)
Interrupt ID
Bit
Interrupt ID
Bit (Note 5)
0
0
FIFOs
FIFOs
Enabled
(Note 5)
Enabled
(Note 5)
XMIT FIFO
Reset
DMA Mode
Select
(Note 6)
Reserved
Reserved
RCVR Trigger RCVR Trigger
LSB
MSB
Number of
Stop Bits
(STB)
OUT1
(Note 3)
Parity Enable Even Parity
Stick Parity
0
Set Break
Divisor Latch
Access Bit
(DLAB)
(PEN)
Select (EPS)
OUT2
Loop
0
0
(Note 3)
Parity Error
Framing Error Break
Transmitter
Holding
Transmitter
Empty
Error in RCVR
FIFO (Note 5)
(PE)
(FE) Interrupt (BI)
Register
(THRE)
(TEMT)
(Note 2)
Trailing Edge Delta Data
Clear to Send Data Set
Ring Indicator Data Carrier
Ring Indicator Carrier Detect (CTS)
Ready (DSR) (RI)
Detect (DCD)
(TERI)
(DDCD)
Bit 2
Bit 2
Bit 10
Bit 3
Bit 3
Bit 11
Bit 4
Bit 4
Bit 12
Bit 5
Bit 5
Bit 13
Bit 6
Bit 6
Bit 14
Bit 7
Bit 7
Bit 15
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART FCR’s is shadowed in the UART1 FIFO Control Shadow Register (Located at offset 0x1A in the in
the Power Control Logical Device, when LD_NUM=0, or Runtime Register Block Logical Device, when LD_NUM=1).
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
92
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
