Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.
Table 6.30 - Baud Rates
DESIRED
BAUD RATE
50
DIVISOR USED TO
PERCENT ERROR DIFFERENCE
HIGH
GENERATE 16X CLOCK
BETWEEN DESIRED AND ACTUAL1 SPEED BIT2
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
0.001
-
-
0.004
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
-
-
0.005
-
-
-
-
-
-
0.030
0.16
0.16
0.16
0.16
32770
32769
1
Note1: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Note 2: The High Speed bit is located in the Device Configuration Space.
SMSC LPC47M182
89
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
