Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 11.11 – Parallel Port Logical Device Configuration Registers
NAME
REG INDEX
DEFINITION
PP Mode Register
0xF0 R/W Note: Bits[2:0] in this register are mapped to 0xF8
register.
Default = 0x3C
on VCC POR,
VTR POR and
HARD RESET
Bits[2:0] Parallel Port Mode
= 100
= 000
= 001
= 101
= 010
= 011
= 111
Printer Mode (default)
Standard and Bi-directional (SPP) Mode
EPP-1.9 and SPP Mode
EPP-1.7 and SPP Mode
ECP Mode
ECP and EPP-1.9 Mode
ECP and EPP-1.7 Mode
Note: Setting Bits[2:0] to either “101”, “011” or “111” will
not change the state of Bits[3:0] in the 0xF8; however,
appropriate Parallel Port mode will be selected.
Bit[6:3] ECP FIFO Threshold
0111b (default)
Bit[7] PP Interupt Type
Not valid when the parallel port is in the Printer
Mode (100) or the Standard & Bi-directional Mode
(000).
= 1 Pulsed Low, released to high-Z.
= 0 IRQ follows nACK when parallel port in EPP Mode
or [Printer,SPP, EPP] under ECP.
IRQ level type when the parallel port is in ECP, TEST,
or Centronics FIFO Mode.
PP Mode Register 2
0xF1 R/W Bits[3:0] Reserved. Set to zero
Bit [4] TIMEOUT_SELECT
= 0 TMOUT (EPP Status Reg.) cleared on write of ‘1’
to TMOUT.
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
= 1 TMOUT cleared on trailing edge of read of EPP
Status Reg.
Bits[7:5] Reserved. Set to zero.
PP Mapping
Register
0xF8 R/W Bits[3:0] Parallel Port Mode. The Bits[3:1] map directly
to Bits[2:0] in the PP Mode Register (0xF0).
= 0001 Standard and Bi-directional (SPP) Mode
= 0010 EPP-1.9 and SPP Mode
= 0100 ECP Mode
Default = 0x08
on VCC POR,
VTR POR and
HARD RESET
= 1000 Printer Mode (default)
= others Reserved
Bits[7:4] Reserved
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
188
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
