Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
is pulled low a period t1 after nSLP_S5 goes high. The period t1 can be as short as 1msec. Typical
measured values are approximately 200msec. The t1 and t2 values are guaranteed by the inherent
design of the system and are not controlled by the LPC47M182.
V_5P0_STBY
nSLP_S3
PWRGD_PS
t2
t1
nBACKFEED_CUT
nSLP_S5
LATCHED_BF_CUT
Figure 7.15 – Latched Backfeed Cut Power Up Sequence
Table 7.45 – Latched Backfeed Cut Power Up Sequence Timing
NAME
t1
DESCRIPTION
nSLP_S5 inactive to nBACKFEED_CUT
MIN
1
TYP
200
MAX
UNITS
msec
active
t2
nSLP_S5 inactive after power rails have
stabilized
25
msec
Note:
Periods t1 and t2 should be guaranteed by the inherent design of the system. These timings are not
controlled by the LPC47M182.
There are two possible timing sequences following the power up signal sequencing. The first possible
sequence is with nSLP_S5 staying high and nBACKFEED_CUT transitioning from low to high, remaining
high for an undetermined period and then going back to low. At this point, the system returns to the end of
the power-up sequence.
During these nBACKFEED_CUT transitions, the propagation delays, rise and fall times for
LATCHED_BF_CUT are as described in the figure below. The first sequence can start at the end of the
power-up sequence at any time.
nSLP_S3
PWRGD_PS
nSLP_S5
nSLP_S5 = 1
nBACKFEED_CUT
Tpropf
Tpropr
Tr
LATCHED_BF_CUT
Tf
Figure 7.16 – Latched Backfeed Cut Sequence 1
SMSC LPC47M182
149
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
SMSC [ SMSC CORPORATION ]
