Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0 =
data, 1 = command). During a host data/command write operation, this bit is set to “1” if SA2 = 1 or
reset to “0” if SA2 = 0.
IBF
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data
register. Setting this flag activates the LPC47M182 CPU’s nIBF (MIRQ) interrupt if enabled. When
the LPC47M182 CPU reads the input data register (DBB), this bit is automatically reset and the
interrupt is cleared. There is no output pin associated with this internal signal.
OBF (Output Buffer Full) - This flag is set to whenever the LPC47M182 CPU write to the output data
register (DBB). When the host system reads the output data register, this bit is automatically reset.
7.25.17 External Clock Signal
The LPC47M182 Keyboard Controller clock source is a 12 MHz clock generated from a 14.318 MHz clock.
The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies to
both internally (Vcc POR) and externally generated reset signals. In powerdown mode, the external clock
signal is not loaded by the chip.
7.25.18 Default Reset Conditions
The LPC47M182 has one source of hardware reset: an external reset via the nPCI_RESET pin. Refer to
Table 7.13 for the effect of each type of reset on the internal registers.
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values
HARDWARE RESET
DESCRIPTION
(nPCI_RESET)
KCLK
KDAT
MCLK
Low
Low
Low
Low
N/A
00H
MDAT
Host I/F Data Reg
Host I/F Status Reg
N/A: Not Applicable
7.25.19 GATEA20 AND KEYBOARD RESET
The LPC47M182 provides two options for GateA20 and Keyboard Reset: 8042 Software Generated
GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
7.26 Port 92 Fast Gatea20 and Keyboard Reset
7.26.1 Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register
(Keyboard Logical Device, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
122
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
