Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Registers INT_GEN1 and INT_GEN2 are enabled to output to the Serial IRQ stream by setting Power
Control Block Configuration Register, at Index 0xF1, Bit [0] to ‘1’. When Bit [0] is set to ‘0’, INT_GEN1 and
INT_GEN2 are prevented from outputting to the Serial IRQ stream.
Writing Bits 0 through 7 to ‘0’ in registers INT_GEN1 and INT_GEN2 enable the corresponding interrupt
(INT1 through INT15) to be asserted (made active) in the Serial IRQ stream. Producing an interrupt in the
Serial IRQ stream by writing these bits to ‘0’ overrides other interrupt sources for the Serial IRQ stream.
No other functional logic in the LPC47M182 sets bits in these registers. The asserted interrupt in the Serial
IRQ stream from registers INT_GEN1 and INT_GEN2 is removed by writing the corresponding bit to ‘1’.
7.25 8042 Keyboard Controller Description
The LPC47M182 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard
management in desktop computer applications. The Universal Keyboard Controller uses an 8042
microcontroller CPU core. This section concentrates on the LPC47M182 enhancements to the 8042. For
general information about the 8042, refer to the “Hardware Description of the 8042” in the 8-Bit Embedded
Controller Handbook.
8042A
LS05
P27
KDAT
KCLK
MCLK
MDAT
P10
P26
TST0
P23
TST1
P22
P11
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ
MIRQ is the Mouse IRQ
Port 21 is used to create a GATEA20 signal from the LPC47M182.
7.25.1 Keyboard Interface
The LPC47M182 LPC interface is functionally compatible with the 8042 style host interface. It consists of
the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output
Data register. Table 7.10 shows how the interface decodes the control signals. In addition to the above
signals, the host interface includes keyboard and mouse IRQs.
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
118
SMSC LPC47M182
DATASHEET
SMSC [ SMSC CORPORATION ]
