Status Register B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and model 30 modes. The
SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a
high impedance state for a read of address 3F1.
PS/2 Mode
7
1
6
1
5
4
3
2
1
0
DRIVE WDATA RDATA WGATE MOT
SEL0 TOGGLE TOGGLE
MOT
EN0
EN1
RESET
COND.
1
1
0
0
0
0
0
0
BIT 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface output pin. This bit is low after a PCI reset and unaffected by a software
reset.
BIT 1 MOTOR ENABLE 1
Active high status of the MTR1 disk interface output pin. This bit is low after a PCI reset and unaffected by a software
reset.
BIT 2 WRITE GATE
Active high status of the WGATE disk interface output.
BIT 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes this bit to change state.
BIT 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes this bit to change state.
BIT 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a PCI reset and it is
unaffected by a software reset.
BIT 6 RESERVED
Always read as a logic "1".
BIT 7 RESERVED
Always read as a logic "1".
PS/2 Model 30 Mode
7
6
5
4
3
2
1
0
nDRV2 nDS1
nDS0 WDATA RDATA WGATE nDS3
nDS2
F/F
F/F
F/F
0
RESET
COND.
N/A
1
1
0
0
1
1
BIT 0 nDRIVE SELECT 2
The DS2 disk interface is not supported.
BIT 1 nDRIVE SELECT 3
The DS3 disk interface is not supported.
BIT 2 WRITE GATE
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is
cleared by the read of the DIR register.
BIT 3 READ DATA
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is
cleared by the read of the DIR register.
SMSC DS – LPC47S45x
Page 30 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
