Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it
up into 8-bit transfers.
See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O
Read and Write cycles.
DMA Read and Write Cycles
DMA read cycles involve the transfer of data from the host (main memory) to the LPC47S45x. DMA write cycles
involve the transfer of data from the LPC47S45x to the host (main memory). Data will be coming from or going to a
FIFO and will have minimal Sync times. Data transfers to/from the LPC47S45x are 1, 2 or 4 bytes.
See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the
sequence of the DMA Read and Write cycles.
DMA Protocol
DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47S45x and special encodings on
LAD[3:0] from the host.
The DMA mechanism for the LPC bus is described in the following Low Pin Count (LPC) Interface Specification
Revision 1.0.
6.3.2 POWER MANAGEMENT
CLOCKRUN Protocol
The CLKRUN# pin is not implemented in the LPC47S45x.
See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1.
LPCPD Protocol
See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.
SYNC Protocol
See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a table of valid SYNC values.
Typical Usage
The SYNC pattern is used to add wait states. For read cycles, the LPC47S45x immediately drives the SYNC pattern
upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47S45x needs to
assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or
1001. The LPC47S45x will choose to assert 0101 or 0110, but not switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.
The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few
clocks. The LPC47S45x uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP
cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47S45x uses a
SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
SYNC Timeout
The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it
will abort the cycle.
SMSC DS – LPC47S45x
Page 26 of 259
Rev. 07/09/2001
DATASHEET
SMSC [ SMSC CORPORATION ]
