REG OFFSET
(hex)
NAME
DESCRIPTION
Fan Tachometer
Register
59
Fan Tachometer Register
Bit[7:0] The 8-bit FAN tachometer count. The number of counts of
the internal clock per pulse of the fan. The count value is
computed from Equation 1 in the Fan section. This value is the
final (maximum) count of the previous pulse (latched). The value in
this register may not be valid for up to 2 pulses following a write to
the preload register.
(R)
Default = 0x00
on VTR POR
Fan Preload Register
5B
(R/W)
5D
Fan Preload Register
Bit[7:0] The FAN tachometer preload. This is the initial value used
in the computation of the FAN count. Writing this register resets
the tachometer count.
Default = 0x00
on VTR POR
LED1
Bit[1:0] LED1 Control
00=off
Default = 0x00
on VTR POR
(R/W)
01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
LED2
5E
Bit[1:0] LED2 Control
00=off
Default = 0x01
on VTR POR
(R/W)
01=Blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ Hz rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
Keyboard Scan
Code
5F
Keyboard Scan Code
Bit[0] LSB of Scan Code
(R/W)
. . .
Default = 0x00
on VTR POR
. . .
. . .
Bit[7] MSB of Scan Code
PM1_CNTRL1
60
Power Management 1 Control Register 1 (PM1_CNTRL 1)
Default = 0x00
on Vbat POR
R/W
Bit[0] SCI_EN
When this bit is set, then the enabled PM1 and GPE1 power
management events will generate an nIO_PME interrupt. When
this bit is reset power management events will not generate an
nIO_PME interrupt. Instead, it will generate an SMI if the
SMI_SCI_EN bit is cleared. This bit does not affect the power
button or RTC wakeup event. This bit also does not affect GPE1
wakeup events.
Bits[7:1] Reserved. These bits always return a value 0.
SMSC LPC47S45x
Page 184 of 259
Rev. 06-01-06
DATASHEET
SMSC [ SMSC CORPORATION ]
