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LPC47M14B-NC 参数 Datasheet PDF下载

LPC47M14B-NC图片预览
型号: LPC47M14B-NC
PDF下载: 下载PDF文件 查看货源
内容描述: 128 PIN ENGANCED超级I / O与LPC接口和USB集线器控制器 [128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB]
分类和应用: 控制器PC
文件页数/大小: 205 页 / 1208 K
品牌: SMSC [ SMSC CORPORATION ]
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BIT 0 nHIGH DENS  
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are  
selected.  
BITS 1 - 2 DATA RATE SELECT  
These bits control the data rate of the floppy controller. See Table 9 for the settings corresponding to the individual  
data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a  
hardware reset.  
BITS 3 - 6 UNDEFINED  
Always read as a logic "1"  
BIT 7 DSKCHG  
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value  
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).  
Model 30 Mode  
7
6
0
5
0
4
0
3
2
1
0
DSK  
DMAEN NOPREC DRATE DRATE  
CHG  
N/A  
SEL1  
1
SEL0  
0
RESET  
COND.  
0
0
0
0
0
BITS 0 - 1 DATA RATE SELECT  
These bits control the data rate of the floppy controller. See Table 9 for the settings corresponding to the individual data  
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.  
BIT 2 NOPREC  
This bit reflects the value of NOPREC bit set in the CCR register.  
BIT 3 DMAEN  
This bit reflects the value of DMAEN bit set in the DOR register bit 3.  
BITS 4 - 6 UNDEFINED  
Always read as a logic "0"  
BIT 7 DSKCHG  
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value  
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).  
CONFIGURATION CONTROL REGISTER (CCR)  
Address 3F7 WRITE ONLY  
PC/AT and PS/2 Modes  
7
6
5
4
3
2
1
0
DRATE DRATE  
SEL1  
1
SEL0  
0
RESET  
COND.  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
BIT 0 and 1 DATA RATE SELECT 0 and 1  
These bits determine the data rate of the floppy controller. See Table 9 for the appropriate values.  
SMSC DS – LPC47M14X  
Page 36  
Rev. 03/19/2001  
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