欢迎访问ic37.com |
会员登录 免费注册
发布采购

LPC47M14B-NC 参数 Datasheet PDF下载

LPC47M14B-NC图片预览
型号: LPC47M14B-NC
PDF下载: 下载PDF文件 查看货源
内容描述: 128 PIN ENGANCED超级I / O与LPC接口和USB集线器控制器 [128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB]
分类和应用: 控制器PC
文件页数/大小: 205 页 / 1208 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LPC47M14B-NC的Datasheet PDF文件第30页浏览型号LPC47M14B-NC的Datasheet PDF文件第31页浏览型号LPC47M14B-NC的Datasheet PDF文件第32页浏览型号LPC47M14B-NC的Datasheet PDF文件第33页浏览型号LPC47M14B-NC的Datasheet PDF文件第35页浏览型号LPC47M14B-NC的Datasheet PDF文件第36页浏览型号LPC47M14B-NC的Datasheet PDF文件第37页浏览型号LPC47M14B-NC的Datasheet PDF文件第38页  
MAIN STATUS REGISTER  
Address 3F4 READ ONLY  
The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register  
can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It  
should be read before each byte transferring to or from the data register except in DMA mode. No delay is required  
when reading the MSR after a data transfer.  
7
6
5
4
3
2
1
0
NON  
DMA  
CMD  
DRV1  
BUSY  
DRV0  
BUSY  
BUSY  
RQM  
DIO  
Reserved Reserved  
BIT 0 - 1 DRV x BUSY  
These bits are set to 1s when a drive is in the seek portion of a command, including implied and overlapped seeks and  
recalibrates.  
BIT 4 COMMAND BUSY  
This bit is set to a 1 when a command is in progress. This bit will go active after the command byte has been accepted  
and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is  
returned to a 0 after the last command byte.  
BIT 5 NON-DMA  
Reserved, read ‘0’. This part does not support non-DMA mode.  
BIT 6 DIO  
Indicates the direction of a data transfer once a RQM is set. A 1 indicates a read and a 0 indicates a write is required.  
BIT 7 RQM  
Indicates that the host can transfer data if set to a 1. No access is permitted if set to a 0.  
DATA REGISTER (FIFO)  
Address 3F5 READ/WRITE  
All command parameter information, disk data and result status are transferred between the host processor and the  
floppy disk controller through the Data Register.  
Data transfers are governed by the RQM and DIO bits in the Main Status Register.  
The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware  
compatibility. The default values can be changed through the Configure command (enable full FIFO operation with  
threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk  
error. Table 12 gives several examples of the delays with a FIFO.  
The data is based upon the following formula:  
Threshold # x  
1
x 8  
-
1.5 µs  
=
DATA  
RATE  
DELAY  
At the start of a command, the FIFO action is always disabled and command parameters must be sent based upon the  
RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that  
invalid data is not transferred.  
SMSC DS – LPC47M14X  
Page 34  
Rev. 03/19/2001  
 复制成功!