An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current
sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result
phase may be entered.
Table 12 – FIFO Service Delay
FIFO THRESHOLD
EXAMPLES
MAXIMUM DELAY TO SERVICING AT
2 Mbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 4 µs - 1.5 µs = 2.5 µs
2 x 4 µs - 1.5 µs = 6.5 µs
8 x 4 µs - 1.5 µs = 30.5 µs
15 x 4 µs - 1.5 µs = 58.5 µs
FIFO THRESHOLD
EXAMPLES
MAXIMUM DELAY TO SERVICING AT
1 Mbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 8 µs - 1.5 µs = 6.5 µs
2 x 8 µs - 1.5 µs = 14.5 µs
8 x 8 µs - 1.5 µs = 62.5 µs
15 x 8 µs - 1.5 µs = 118.5 µs
FIFO THRESHOLD
EXAMPLES
MAXIMUM DELAY TO SERVICING AT
500 Kbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 16 µs - 1.5 µs = 14.5 µs
2 x 16 µs - 1.5 µs = 30.5 µs
8 x 16 µs - 1.5 µs = 126.5 µs
15 x 16 µs - 1.5 µs = 238.5 µs
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DSK
CHG
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
PS/2 Mode
7
6
1
5
1
4
1
3
1
2
1
0
DSK
DRATE DRATE nHIGH
CHG
SEL1
N/A
SEL0 DENS
N/A
RESET
COND.
N/A
N/A
N/A
N/A
N/A
1
SMSC DS – LPC47M14X
Page 35
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
