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LPC47M14B-NC 参数 Datasheet PDF下载

LPC47M14B-NC图片预览
型号: LPC47M14B-NC
PDF下载: 下载PDF文件 查看货源
内容描述: 128 PIN ENGANCED超级I / O与LPC接口和USB集线器控制器 [128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB]
分类和应用: 控制器PC
文件页数/大小: 205 页 / 1208 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LPC47M14B-NC的Datasheet PDF文件第25页浏览型号LPC47M14B-NC的Datasheet PDF文件第26页浏览型号LPC47M14B-NC的Datasheet PDF文件第27页浏览型号LPC47M14B-NC的Datasheet PDF文件第28页浏览型号LPC47M14B-NC的Datasheet PDF文件第30页浏览型号LPC47M14B-NC的Datasheet PDF文件第31页浏览型号LPC47M14B-NC的Datasheet PDF文件第32页浏览型号LPC47M14B-NC的Datasheet PDF文件第33页  
BIT 3 READ DATA TOGGLE  
Every inactive edge of the RDATA input causes this bit to change state.  
BIT 4 WRITE DATA TOGGLE  
Every inactive edge of the WDATA input causes this bit to change state.  
BIT 5 DRIVE SELECT 0  
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset  
and it is unaffected by a software reset.  
BIT 6 RESERVED  
Always read as a logic "1".  
BIT 7 RESERVED  
Always read as a logic "1".  
PS/2 Model 30 Mode  
7
6
5
4
3
2
1
0
nDRV2 nDS1  
nDS0 WDATA RDATA WGATE nDS3  
nDS2  
F/F  
0
F/F  
0
F/F  
0
RESET  
COND.  
N/A  
1
1
1
1
BIT 0 nDRIVE SELECT 2  
The DS2 disk interface is not supported.  
BIT 1 nDRIVE SELECT 3  
The DS3 disk interface is not supported.  
BIT 2 WRITE GATE  
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is  
cleared by the read of the DIR register.  
BIT 3 READ DATA  
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is  
cleared by the read of the DIR register.  
BIT 4 WRITE DATA  
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and  
is cleared by the read of the DIR register. This bit is not gated with WGATE.  
BIT 5 nDRIVE SELECT 0  
Active low status of the DS0 disk interface output.  
BIT 6 nDRIVE SELECT 1  
Active low status of the DS1 disk interface output.  
BIT 7 nDRV2  
Active low status of the DRV2 disk interface input. Note: This function is not supported.  
DIGITAL OUTPUT REGISTER (DOR)  
Address 3F2 READ/WRITE  
The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the  
DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be  
written to at any time.  
7
6
5
4
3
2
1
0
MOT  
MOT  
MOT  
MOT  
DMAEN  
nRESET  
DRIVE  
DRIVE  
EN3  
EN2  
EN1  
EN0  
SEL1  
SEL0  
RESET  
COND.  
0
0
0
0
0
0
0
0
SMSC DS – LPC47M14X  
Page 29  
Rev. 03/19/2001  
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