5.5 INTERNAL PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface
as Vcc cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc > 2.3V (nominal), and the
LPC47M14x host interface is active. When the internal PWRGOOD signal is “0” (inactive), Vcc ≤ 2.3V (nominal), and
the LPC47M14x host interface is inactive; that is, LPC bus reads and writes will not be decoded.
The LPC47M14x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2, USB+, USB-, PD[4:1]+,
PD[4:1]- and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD
signal has gone inactive, since VTR must always be powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and
GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive. See “Trickle Power
Functionality” section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout.
5.6 32.768 KHZ TRICKLE CLOCK INPUT
The LPC47M14x utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink,
wake on specific key function, and to the USB Hub to support suspend and resume signaling.
5.7 TRICKLE POWER FUNCTIONALITY
When the LPC47M14x is running under VTR only (VCC removed), PME wakeup events are active and (if enabled)
able to assert the nIO_PME pin active low. The following lists the wakeup events:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
UART 1 Ring Indicator
UART 2 Ring Indicator
Keyboard data
Mouse data
“Wake on Specific Key” Logic
Fan Tachometers (Note)
GPIOs for wakeup. See below.
Event on USB Downstream/Upstream ports
Note: The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan
tachometers before removing fan power.
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant:
ꢀ
I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may
only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.
ꢀ
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by
VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.
The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41,
GP43, GP50-GP57, GP60, and GP61. These GPIOs function as follows (with the exception of GP53, GP60 and
GP61 - see below):
ꢀ
Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load
on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins
have input buffers into the wakeup logic that are powered by VTR.
All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be
used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs and low
following a VCC POR and Hard Reset. GP53 cannot be used for wakeup under VTR power since this is the IRTX pin
which comes up as output and low following a VTR POR, a VCC POR and Hard Reset. Also, GP32 and GP33 revert
to their non-inverting GPIO input function when VCC is removed from the part. GP43 reverts to the basic GPIO
function when VCC is removed from the part, but its programmed input/output, invert/non-invert and output buffer
type is retained.
The other GPIOs function as follows:
GP36, GP37 and GP40:
ꢀ
Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input
buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.
SMSC DS – LPC47M14X
Page 18
Rev. 03/19/2001
SMSC [ SMSC CORPORATION ]
