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LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
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2. End of Seek, Relative Seek, or Recalibrate command  
3. FDC requires a data transfer during the execution phase in the non-DMA mode  
The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0,  
identifies the cause of the interrupt.  
Table 25 - Interrupt Identification  
SE  
0
1
IC  
11  
00  
INTERRUPT DUE TO  
Polling  
Normal termination of Seek or  
Recalibrate command  
1
01  
Abnormal termination of Seek  
or Recalibrate command  
The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must  
be issued immediately after these commands to terminate them and to provide verification of the head position (PCN).  
The H (Head Address) bit in ST0 will always return a "0". If a Sense Interrupt Status is not issued, the drive will continue  
to be BUSY and may affect the operation of the next command.  
Sense Drive Status  
Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase  
from the command phase. Status Register 3 contains the drive status information.  
Specify  
The Specify command sets the initial values for each of the three internal times. The HUT (Head Unload Time) defines  
the time from the end of the execution phase of one of the read/write commands to the head unload state. The SRT  
(Step Rate Time) defines the time interval between adjacent step pulses. Note that the spacing between the first and  
second step pulses may be shorter than the remaining step pulses. The HLT (Head Load Time) defines the time  
between when the Head Load signal goes high and the read/write operation starts. The values change with the data  
rate speed selection and are documented in Table 26. The values are the same for MFM and FM.  
The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA mode is selected,  
and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are signaled by the DMA request cycles.  
Non-DMA mode uses the RQM bit and the interrupt to signal data transfers.  
Configure  
The Configure command is issued to select the special features of the FDC. A Configure command need not be issued  
if the default values of the FDC meet the system requirements.  
Table 26 - Drive Control Delays (ms)  
HUT  
SRT  
2M  
64  
4
..  
56  
60  
1M  
128  
8
..  
112  
120  
500K 300K 250K  
2M  
4
3.75  
..  
0.5  
0.25  
1M  
8
7.5  
..  
1
0.5  
500K 300K 250K  
0
1
..  
E
F
256  
16  
..  
426  
26.7  
..  
512  
32  
..  
16  
15  
..  
26.7  
25  
..  
32  
30  
..  
224  
240  
373  
400  
448  
480  
2
1
3.33  
1.67  
4
2
HLT  
2M  
64  
0.5  
1
1M  
128  
1
2
..  
500K  
256  
2
4
..  
300K  
426  
3.3  
6.7  
..  
250K  
512  
4
8
.
00  
01  
02  
..  
..  
7F  
7F  
63  
63.5  
126  
127  
252  
254  
420  
423  
504  
508  
Page 51  
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