欢迎访问ic37.com |
会员登录 免费注册
发布采购

LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号LPC47M10X_07的Datasheet PDF文件第50页浏览型号LPC47M10X_07的Datasheet PDF文件第51页浏览型号LPC47M10X_07的Datasheet PDF文件第52页浏览型号LPC47M10X_07的Datasheet PDF文件第53页浏览型号LPC47M10X_07的Datasheet PDF文件第55页浏览型号LPC47M10X_07的Datasheet PDF文件第56页浏览型号LPC47M10X_07的Datasheet PDF文件第57页浏览型号LPC47M10X_07的Datasheet PDF文件第58页  
2. The write pre-compensation given to a perpendicular mode drive will be 0ns.  
3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed  
write pre-compensation.  
Note: Bits D0-D3 can only be overwritten when OW is programmed as a "1".If either GAP or WGATE is a "1" then D0-  
D3 are ignored.  
Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:  
1. "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected  
and retain their previous value.  
2. "Hardware" resets will clear all bits  
(GAP, WGATE and D0-D3) to "0", i.e all conventional mode.  
Table 27 - Effects of WGATE and GAP Bits  
PORTION OF  
GAP 2  
LENGTH OF  
GAP2 FORMAT  
FIELD  
WRITTEN BY  
WRITE DATA  
OPERATION  
0 Bytes  
WGATE GAP  
MODE  
Conventional  
Perpendicular  
(500 Kbps)  
Reserved  
(Conventional)  
Perpendicular  
(1 Mbps)  
0
0
0
1
22 Bytes  
22 Bytes  
19 Bytes  
1
1
0
1
22 Bytes  
41 Bytes  
0 Bytes  
38 Bytes  
LOCK  
In order to protect systems with long DMA latencies against older application software that can disable the FIFO the  
LOCK Command has been added. This command should only be used by the FDC routines, and application software  
should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should  
be used.  
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command  
can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS  
by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware"  
RESET from the nPCI_RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to  
their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value  
of the LOCK bit set by the command byte.  
ENHANCED DUMPREG  
The DUMPREG command is designed to support system run-time diagnostics and application software development  
and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth  
byte of the DUMPREG command has been modified to contain the additional data from these two commands.  
COMPATIBILITY  
The LPC47M10x was designed with software compatibility in mind. It is a fully backwards- compatible solution with the  
older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as  
well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions  
and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the  
IDENT and MFM bits are configured by the system BIOS.  
Page 54  
 复制成功!