I/O and DMA START Fields
I/O and DMA cycles use a START field of 0000.
Reset Policy
The following rules govern the reset policy:
1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the
removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable
that is used for the PCI bus.
2) When nPCI_RESET goes active (low):
a) the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal.
b) the LPC47M10x must ignore nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive
(high).
ELECTRICAL SPECIFICATIONS
The LPC interface uses 3.3V signaling. No output from the LPC47M10x drives higher than 3.3V nominal.
The electrical characteristics of each signal is described below.
LAD[3:0]
The AC and DC specifications for these signals are the same as defined for AD[31:0] in section 4.2.2 of the “PCI
Local Bus Specification, Rev 2.1”. That section contains the specifications for the 3.3V signaling environment.
The LAD[3:0] signals go high during the TAR phase. The last device driving the LAD[3:0] is responsible to drive the
signals high during the first clock of the TAR phase. During the second clock, neither the host nor the LPC47M10x
will drive LAD[3:0] (LAD[3:0] is floated).
Weak pull-up resistors of 10k-100k ohms will be included on LAD[3:0] to keep the signals high. These pull-ups are
external to the LPC47M10x.
nLDRQ
The AC and DC specifications for these signals are the same as for non-shared signals as defined in section 4.2.2 of
the “PCI Local Bus Specification, Rev 2.1”. That section contains the specifications for the 3.3V signaling
environment.
nLDRQ is a standard output from the LPC47M10x and a standard input to the host.
nLPCPD
The host drives this signal as a standard 3.3V output.
nLFRAME
The host drives this signal as a standard 3.3V output.
nPCI_RESET
The host drives this signal as a standard 3.3V output.
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