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LPC47M10X_07 参数 Datasheet PDF下载

LPC47M10X_07图片预览
型号: LPC47M10X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 100引脚增强型超级I / O控制器, LPC接口为消费类应用 [100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications]
分类和应用: 控制器PC
文件页数/大小: 188 页 / 1031 K
品牌: SMSC [ SMSC CORPORATION ]
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BIT 6 DMA REQUEST  
Active high status of the DMA request pending.  
BIT 7 INTERRUPT PENDING  
Active high bit indicating the state of the Floppy Disk Interrupt.  
STATUS REGISTER B (SRB)  
Address 3F1 READ ONLY  
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB  
can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high  
impedance state for a read of address 3F1.  
PS/2 Mode  
7
1
6
1
5
4
3
2
1
0
MOT  
EN0  
0
DRIVE WDATA RDATA WGATE MOT  
SEL0 TOGGLE TOGGLE  
EN1  
0
RESET  
COND.  
1
1
0
0
0
0
BIT 0 MOTOR ENABLE 0  
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a  
software reset.  
BIT 1 MOTOR ENABLE 1  
Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a  
software reset.  
BIT 2 WRITE GATE  
Active high status of the WGATE disk interface output.  
BIT 3 READ DATA TOGGLE  
Every inactive edge of the RDATA input causes this bit to change state.  
BIT 4 WRITE DATA TOGGLE  
Every inactive edge of the WDATA input causes this bit to change state.  
BIT 5 DRIVE SELECT 0  
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset  
and it is unaffected by a software reset.  
BIT 6 RESERVED  
Always read as a logic "1".  
BIT 7 RESERVED  
Always read as a logic "1".  
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